The present invention relates, in general, to electronics, and more particularly, to semiconductor devices and methods of forming semiconductor devices.
In the past, the semiconductor industry utilized various methods and structures to form electrical connections to a semiconductor die or semiconductor device. For example, wire bonding was one technique used to form an electrical connection between a bonding pad on the semiconductor die and an attachment point on a leadframe of a semiconductor package. Typically, the bonding pad was formed in a non-active area of the semiconductor die. Leadless connection techniques, such as solder balls or flip chip techniques, applied spheres or balls of solder to a bonding pad or other type of connection platform of a semiconductor die. The solder balls were thereafter placed in contact with conductors on a printed circuit board or other type of supporting substrate and soldered to the conductors. In some cases, and particularly in leadless applications such as flip chip, connection platforms were formed in an active area of the semiconductor die. Often, it was desirable to route conductors from the connection platform to a different portion of the semiconductor die in order to facilitate forming the leadless or other type of connection to the semiconductor die.
FIG. 1 through FIG. 3 illustrate some steps in a typical prior art method for routing electrical connection from a connection platform 22 to another area of a semiconductor die 20. Typically, a semiconductor substrate 21 had a connection platform 22 formed somewhere on the surface of substrate 21. A passivation dielectric 23 generally was formed on the surface of semiconductor die 20. An inter-layer dielectric 24 was formed overlying passivation dielectric 23 and over a portion of platform 22. Semiconductor processing techniques were utilized to form dielectric 23 and to form an opening through dielectric 23 to expose a portion of the surface of platform 22. Thereafter, a plating base metal was sputtered on to the exposed portions of platform 22 to form a base 26 that would be used for a subsequent electro-plating operation. The material used for base 26 was a conductor to facilitate the electro-plating and typically was a multilayer metal such layers of aluminum/nickel-vanadium/copper (Al/NiV/Cu), or titanium-tungsten/copper (TiW/Cu), or may be evaporated chrome/copper. Typically, semiconductor processing techniques were used to form a photo-resist mask, not show, that was used in sputtering or evaporating base 26. As is well know in the art, sputtering or evaporating techniques require equipment and procedures that form a vacuum and operate at high temperatures in order to accomplish the sputtering operation. Such equipment, the maintenance thereof, and the operation thereof are expensive. Thereafter, semiconductor processing techniques were again utilized to form a photoresist layer, not shown, covering layer 26 in addition to forming a mask for subsequent electroplating operation. Then, conductor material, such as copper (Cu) or a nickel-gold (NiAu) alloy was electro-plated through an opening in the mask and onto layer 26 in order to form conductor 27. Thereafter, the photo-resist was removed leaving conductor 27 electro-plated onto base 26. Subsequently, semiconductor processing techniques were again utilized to form a dielectric 29 covering electro-plated conductor 27, and to form an opening through dielectric 29 to expose a portion of conductor 27. Thereafter, semiconductor processing techniques were once again utilized to deposit a conductor material into the opening to form an electrical contact 31 to platform 22. The semiconductor processing techniques, sputtering techniques, and electro-plating operations added additional cost to the semiconductor device. Additionally, the cost of the associated equipment and the maintenance of the equipment also added to the costs of the semiconductor device.
Accordingly, it is desirable to have a method of forming an electrical contact to a semiconductor device that does not require semiconductor processing techniques and equipment, that does not require sputtering, that does not utilize each electro-plating, and that has a low cost.
For simplicity and clarity of illustration, elements in the figures are not necessarily to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description.